akd8181d pattern a pattern b akd818 1d ak818 1d evaluation board the akd8181 d is an evaluation board for ak8181 d . therefore, it is easy to evaluate dc/ac characteristics and confirm product functions. - sma terminal of the differntial input - enable to construct input load circuit for interface - enable to construct three types of output load circuit - preparing terminal and land pattern for vdd/v ss/vdd - 2v - clk_sel and clk_en control switch power there are the following t if you have configured a termination circuit with resistor only (pattern b or c), it becomes possible to - - - clock input input vdd v ss vdd - 2v clk_en sw p clk 0p/n i nput p clk 1p/n i nput output load clk_ s e l sw output pin q0 - 3 /q0n - 3n in put interface load akd8181d-e-00 1 2012/12
akd8181d pattern a ncno components pattern b b vss vss zo=50 zo=50 vss vss zo=50 zo=50 power there are the following t hree power supplies. if you have configured a termination circuit with resistor only (pattern b or c), it becomes possible to evaluate even without applying power to the vdd - 2v terminal. - vdd the core power supply of ak8181 d (3.3v) - v ss the core power supply of ak8181 d (gnd) - vdd - 2v power supply for the end of the output load resistor (=vdd - 2v) clock input ak8181 d inputs the clock selected by clk_sel switch . ( differential input or lvpecl ) the clock input signal can terminate if needed . note) gnd of the sma terminal is connected to the v ss inside the substrate. input load circuit for interface i t can construct interface load circuit for input differential clock. examples are shown below. the state of initial shipment is pattern c . akd8181d-e-00 2 2012/12
akd8181d pattern c pattern d pattern e vss vss zo=50 zo=50 0 vss vss zo=50 zo=50 0 vss vss zo=50 zo=50 5 0 akd8181d-e-00 3 2012/12
akd8181d pattern a with applying power to the vdd-2v terminal pattern b b ?#?? ???!? >?
? ? ??%???>? ??#?? >? ?>? ??>?>e>e>>t?>? ?? ????
? pattern c b ?#?? ???!? >?
? ? ??%???>? ??#?? >? ?>? ??>?>e>e>>t?>? ?? ????
? b q0,1,2,3 q0n,1n, 2n,3n rtt 0.1uf 0 0 zo=50 zo=50 q0,1,2,3 q0n,1n, 2n,3n zo=50 zo=50 short short q0,1,2,3 q0n,1n, 2n,3n 0 0 zo=50 zo=50 0 ??? = 1 ( ( ? ?? + ? ?? ) / ( ??? ? 2 ) ) ? 0 output load circuit it can terminate by the following t hree methods. (pattern a/b /c ) the state of initial shipment is pattern a . akd8181d-e-00 4 2012/12
1 1 2 2 3 3 4 4 5 5 a a b b c c d d AK8181D_evaluation_board z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 h:pclk1p,pclk1n l:pclk0p,pclk0n l:off h:on z o = 5 0 z o = 5 0 z o = 5 0 z o = 5 0 l:dis h:en 5mm x 5mm 5mm x 5mm 5mm x 5mm z o = 5 0 v d d v d d v d d v d d v d d v d d v d d v d d v d d v d d v d d v d d t i t l e s i z e d o c u m e n t n u m b e r r e v d a t e : s h e e t o f AK8181D 1 . 0 AK8181D_evaluation_board a 3 1 2 t u e s d a y , f e b r u a r y 2 6 , 2 0 1 3 t i t l e s i z e d o c u m e n t n u m b e r r e v d a t e : s h e e t o f AK8181D 1 . 0 AK8181D_evaluation_board a 3 1 2 t u e s d a y , f e b r u a r y 2 6 , 2 0 1 3 t i t l e s i z e d o c u m e n t n u m b e r r e v d a t e : s h e e t o f AK8181D 1 . 0 AK8181D_evaluation_board a 3 1 2 t u e s d a y , f e b r u a r y 2 6 , 2 0 1 3 s m a 1 c l k _ e n 1 2 3 4 5 r 2 4 o p e n p 2 2 t p 1 p 2 4 v d d - 2 v t p 1 r 3 2 4 9 . 9 p 1 2 t p 1 r 2 8 o p e n r 3 1 o p e n r 3 8 4 9 . 9 r 1 5 o p e n c 4 0 . 1 u p 4 t p 1 r 1 4 9 . 9 r 3 4 4 9 . 9 ic1 AK8181D v s s 1 c l k _ e n 2 c l k _ s e l 3 p c l k 0 p 4 p c l k 0 n 5 p c l k 1 p 6 p c l k 1 n 7 n c 9 v d d 1 0 q 3 n 1 1 q 3 1 2 v d d 1 3 q 2 n 1 4 q 2 1 5 q 1 n 1 6 q 1 1 7 v d d 1 8 q 0 n 1 9 q 0 2 0 n c 8 c 1 0 . 0 1 u p 2 0 t p 1 c 2 0 . 1 u r 4 4 4 9 . 9 s m a 3 p c l k 0 n 1 2 3 4 5 c 1 2 o p e n r 9 o p e n t p 2 c l k _ s e l r 2 7 o p e n r 3 o p e n c 7 0 . 1 u r 4 1 o p e n p 2 1 t p 1 r 2 o p e n r 3 3 o p e n r 3 6 o p e n p 1 4 t p 1 r 1 2 o p e n r 3 0 o p e n p 6 t p 1 c 8 0 . 1 u r 3 5 0 r 2 5 0 s w 3 o e 1 1 2 o e 3 3 c 6 0 . 1 u r 2 2 o p e n r 1 9 o p e n p 2 3 v d d - 2 v t p 1 r 4 3 o p e n p 8 t p 1 p 1 3 t p 1 c 1 0 0 . 1 u p 5 t p 1 r 4 o p e n c 1 1 o p e n p 1 9 t p 1 r 4 2 o p e n r 3 7 4 9 . 9 r 1 8 4 9 . 9 r 7 4 9 . 9 p 2 t p 1 r 6 o p e n p 1 6 t p 1 r 2 1 4 9 . 9 r 3 9 o p e n c 9 0 . 1 u p 7 t p 1 r 2 0 0 p 1 1 t p 1 p 1 0 t p 1 c 5 0 . 0 1 u r 5 o p e n p 1 7 t p 1 p 2 5 v d d - 2 v t p 1 r 2 3 o p e n r 1 0 0 s w 1 c l k _ e n 1 h 2 c l k _ e n 3 l t p 1 c l k _ e n r 8 4 9 . 9 s m a 5 p c l k 1 n 1 2 3 4 5 r 2 9 o p e n r 1 3 o p e n s m a 2 p c l k 0 p 1 2 3 4 5 t p 3 o e s w 2 c l k _ s e l 1 1 2 c l k _ s e l 3 3 r 2 6 4 9 . 9 p 3 t p 1 r 4 0 o p e n r 1 7 4 9 . 9 p 9 t p 1 p 1 8 t p 1 r 1 4 o p e n r 1 6 o p e n s m a 4 p c l k 1 p 1 2 3 4 5 p 1 5 t p 1 r 1 1 4 9 . 9 c 3 0 . 0 1 u p 1 t p 1
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vdd-2v 5mm x 5mm 5mm x 5mm 5mm x 5mm v d d t i t l e s i z e d o c u m e n t n u m b e r r e v d a t e : s h e e t o f power 1 . 0 AK8181D_evaluation_board a 2 2 m o n d a y , d e c e m b e r 0 3 , 2 0 1 2 t i t l e s i z e d o c u m e n t n u m b e r r e v d a t e : s h e e t o f power 1 . 0 AK8181D_evaluation_board a 2 2 m o n d a y , d e c e m b e r 0 3 , 2 0 1 2 t i t l e s i z e d o c u m e n t n u m b e r r e v d a t e : s h e e t o f power 1 . 0 AK8181D_evaluation_board a 2 2 m o n d a y , d e c e m b e r 0 3 , 2 0 1 2 c 1 5 2 2 u p 2 6 v d d - 2 v t p 1 p 2 7 v d d t p 1 t p 6 v s s p 2 8 v s s t p 1 c 1 3 2 2 u t p 4 v d d - 2 v c 1 4 1 u t p 5 v d d
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